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MAX34565
12V Hot-Plug Switch in TDFN Package
Latchoff Version
Once the latchoff version has entered thermal shutdown,
it does not attempt to turn back on. The only way to turn
this device back on is to cycle the power to the device.
When power is reapplied ton the V CC pad, the junction
temperature needs to be less than T SHDN for the device
to be enabled.
Applications Information
Exposed Pad (V CC )
The exposed pad is the voltage supply pin for the device
and should be connected to a large trace or plane. The
exposed pad also acts as a heatsink, and can dissipate
heat from the device.
R ILIM . To greatly reduce this offset, it is recommended
that one of the LOAD pins have a dedicated connection
to ILIM though R ILIM , and not be used to pass the LOAD
current, I LOAD ( Figure 6 ). This would leave four LOAD
pins to pass I LOAD , which should be sufficient. Because
there is only a small amount of current passed from this
lone LOAD pin to ILIM, there is a negligible voltage offset
applied to the internal comparator. This method is the
best way to attain an accurate current limit for I LOAD .
V CC
Decoupling Capacitors
It is of utmost importance to properly bypass the device’s
supply pins. A decoupling capacitor absorbs the energy
stored in the supply and board parasitic inductance when
the FET is turned off, thereby reducing the magnitude of
overshoot of V CC . This can be accomplished by using a
high-quality (low ESR, low ESL) ceramic capacitor sol-
dered directly between the V CC and GND connections.
Any series resistance with this bypass capacitor lowers
its effectiveness and is not recommended. A minimum
0.5 F F ceramic capacitor is required ( Figure 5 ). However,
0.5μF
MINIMUM
REQUIRED
MAX34565
GND
2 ? TO 10 ?
RECOMMENDED
depending on the parasitic inductances present in the
end application, a larger capacitor could be necessary.
Current Limiting Resistor
A small resistor (2 I to 10 I ) in series with the GND pin of
the device limits current flow during momentary reverse
BOARD GROUND
Figure 5. Power Conditioning Circuit
avalanche break down, and consequently limits total
parasitic charge injected into the device ( Figure 5 ). If this
method is used, it is imperative that the bypass capaci-
LOAD
LOAD
TO APPLICATION
tor be directly across chip V CC and ground connections,
though not through this resistor.
MAX34565
LOAD
LOAD
LOAD and ILIM Connections
Small parasitic resistances in the bond wires of the LOAD
pins and in the traces connected to the LOAD pins can
result in a voltage offset while current is flowing. Since
the voltage drop across R ILIM is used to set the I SCL and
I OVL limits, this induced offset can increase the value of
I SCL and I OVL from the specified values for any given
LOAD
ILIM
Figure 6. LOAD and ILIM Connections
R LIM
8
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